1. Field of the Invention
The present invention relates to a semiconductor memory device which is employed in electronic circuits of various technical fields including office automation apparatuses, household electrical appliances, such as facsimile machines, printers and video cameras, as well as automobiles, power plants and space satellites.
More particularly, the present invention relates to a semiconductor memory device for storing necessary data signals.
2. Related Background Art
FIG. 1 illustrates a semiconductor memory which can be programmed once. The memory cell of this semiconductor memory is made up of a MOS field effect transistor (hereinafter referred to as a `MOSFET`) which is an insulated-gate field effect transistor, and an insulating film.
Such a memory has been described in, for example, "A new Programmable Cell Utilizing Insulator Breakdown" IEDM' 85, pp 639 through 642.
Another type of semiconductor memory is shown in FIG. 2.
In FIG. 2 which is a cross-sectional view thereof, reference numeral 120 denotes a n type substrate; 121, a p.sup.+ drain; 122, a p.sup.+ source; 123, a floating gate; 124, an insulating layer; 125, a drain interconnection; and 126, a source interconnection. The floating gate 123 is manufactured by embedding, for example, a polysilicon into a silicon oxide.
Normally, no current flows between the source and the drain. When a high voltage is applied between the source and drain of this transistor, avalanche breakdown occurs in the pn junction on the side of the drain, injecting electrons of a high energy level to the floating gate and thus permitting current to be established between the source and drain, by which writing can be performed on the memory. When this device is used as a memory, injection and non-injection of electrons to the floating gate are made to correspond to 1 and 0 of data, respectively. However, in the above-described memory, since a slight amount of electric charges stored in the floating gate leaks, permanent storage of data is impossible, and the reading characteristics vary with time.
Furthermore, the aforementioned MOSFET is not suited to the fine processing, and is characterized by a low mutual conductance (gm characteristics).
Furthermore, when the gate length is 0.5 .mu.m or less, improvement in the aforementioned MOSFET based on the scaling rule cannot be expected.
Apart from the above-mentioned semiconductor device, a SOI type MOSFET has also been proposed (Japanese Patent Application Laid-Open No. 2-14578). In this semiconductor device, a SiO.sub.2 layer is provided on a Si substrate, and a Si mesa structure is provided on the SiO.sub.2 layer. A gate oxide film is provided on the side wall of the mesa structure.
FIGS. 3 and 4 illustrate such a device. In FIGS. 3 and 4, reference numeral 232 denotes an insulating film; 231', a crystalline silicon; 236, a source region; 237, a drain region; and 235, a gate electrode which bridges a channel region of the crystalline Si portion. FIG. 3 is a section taken along a line a-a' of FIG. 4. As shown in FIG. 3, upper three surfaces of the crystalline Si 231' portion are covered with the gate electrode 235 through the gate oxide film 234, while a lower surface 238 thereof is in contact with the surface of the insulating film 232. The dimensions of the crystalline Si portion satisfy W.sub.0 &lt;2W.sub.H. Thus, the channel of the side wall is increased, thus increasing the channel conductance.
A MOSFET which is similar to the above-mentioned one in terms of the structure has also been proposed (Japanese Patent Application Laid-Open No. 2-263473).
FIG. 5 is a plan view of this MOSFET. FIG. 6 is a section taken along a line A-A' of FIG. 5. FIG. 7 is a section taken along a line B-B' of FIG. 5. A crystalline Si layer 246 forms a source 243, a drain 242 and a channel. The portion of the crystalline Si layer 246 which is covered by a gate electrode 245 forms a channel region connected to a substrate 240 via an opening 247. The drain layer 242 is connected to the substrate 240 through the crystalline Si layer 246 via an opening 248.
The above-described conventional structures are characterized in an increased leaking current of the transistor, variations in the transistor and degraded OFF characteristics and hence unstable operation of the transistor. First, why off characteristics of the SOI type MOSFET are degraded will be explained. The present inventors consider that it is because the Si region which forms the channel is covered with a SiO.sub.2 except for the interfaces between the source and drain and the Si region. That is, the Si region which forms the channel portion is made completely floating, and the potential thereof cannot be fixed, making the operation unstable. Furthermore, the carriers (electrons in the case of, for example, a p type MOSFET) generated in the Si region when the transistor is in an On state stop flowing when the transistor is turned off, and remain in the Si region until they recombine with holes and disappear, thus deteriorating the off characteristics of the transistor.
In the aforementioned conventional transistors, a large amount of current leaks because the channel region surrounded by the gate electrode is in direct contact with the insulating layer which is the substrate. That is, the channel region is made in a completely depletion state when the transistor is turned on, and the resultant depletion layer reaches the interface between the channel region and the insulating layer and generates a large amount of recombination current by the defects present in the interface.
One of the read-only memories which can be programmed (written) by the user and which can be random accessed is known as bipolar PROM. FIG. 8 illustrates such a memory cell. In FIG. 8, reference numeral 101 denotes bit lines; 102, word lines; 103, a bipolar transistor disposed in a memory cell in which an emitter 105 thereof is connected to the bit line 101, a collector 106 is connected to the word line and a base 104 is made floating; 107, a diode through which the word line 102 is connected to a power source Vcc 108. FIGS. 9A and 9B are cross-sectional views of the bipolar transistor 103 of this memory. In FIGS. 9A and 9B, reference character 110 denotes a p type Si substrate; 111, a n.sup.+ buried layer; 112, a n.sup.- epitaxial layer; 113, a field oxide film; 114, a p type base; 115, a n.sup.+ emitter layer; and 116, an Al interconnection. In the memory, breakage of the diode between the emitter and the base corresponds to binary data. FIG. 9A illustrates the state in which writing is not yet conducted, and FIG. 9B shows the state in which writing has been conducted.
Before writing takes place, the Al interconnection on the n.sup.+ emitter is flat, as indicated by 117. When a large current pulse is applied between the word line and the bit line for writing, an eutectic alloy 118 of aluminum and silicon penetrates the base layer 114 and is made conductive.
However, such a bipolar transistor suffers from drawbacks in that there is a limitation of cell size due to separation of the bipolar transistor and hence a high integration thereof is difficult, and in that the eutectic alloy 118 formed by a large current varies in the cells and therefore stable reading out cannot be obtained. Also, a longitudinally long dynamic random-access memory (DRAM) which employs a surrounding gate transistor (SGT) as an addressing transistor and in which a trench capacitor is formed in the main electrode region thereof which is located close to the substrate has been proposed.
The present inventors found that such a DRAM has the following problems. A high integration of 16M bits or above or fine processing of the cell restricts the capacitor size. Thus, the capacitance of the capacity is reduced, and storage of a large amount of signal electric charges becomes impossible. As a result, the signal finally output when the stored signal is read out by capacitive division is reduced, reducing the S/N ratio. This generates malfunction of the memory.
Furthermore, the manufacturing process is very complicated due to the longitudinally long structure and yield cannot thus be increased. That is, the present inventors came to the conclusion that application of the currently manufactured fine transistors, such as SGT, to a DRAM does not serve its original purpose.